An Empirical High Level Performance Model For Future Many-cores
Abstract
Estimating the potential performance of parallel applications
on the yet-to-be-designed future many cores is very
speculative. The simple models proposed by Amdahl's law
(xed input problem size) or Gustafson's law (xed number
of cores) do not completely capture the scaling behaviour
of a multi-threaded (MT) application leading to over estimation
of performance in the many-core era. On the other
hand, modeling many-core by simulation is too slow to study
the applications performance.
In this paper, we propose a more rened but still tractable,
high level empirical performance model for multi-threaded
applications, the Serial/Parallel Scaling (SPS)Model to study
the scalability and performance of application in many-core
era. SPS model learns the application behavior on a given
architecture and provides realistic estimates of the performance
in future many-cores. Considering both input problem
size and the number of cores in modeling, SPS model can
help in making high level decisions on the design choice of future
many-core applications and architecture. We validate
the model on the Many-Integrated Cores (MIC) xeon-phi
with 240 logical cores.