List Scheduling in Embedded Systems Under Memory Constraints - Inria - Institut national de recherche en sciences et technologies du numérique
Article Dans Une Revue International Journal of Parallel Programming Année : 2015

List Scheduling in Embedded Systems Under Memory Constraints

Résumé

Video decoding and image processing in embedded systems are subject to strong resource constraints, particularly in terms of memory. List-scheduling heuristics with static priorities (HEFT, SDC, etc.) being the oft-cited solutions due to both their good performance and their low complexity, we propose a method aimed at introducing the notion of memory into them. Moreover, we show that through adequate adjustment of task priorities and judicious resort to insertion-based policy, speedups up to 20% can be achieved. We also show that our technique allows to prevent deadlock and to substantially reduce the required memory footprint compared to classic list-scheduling heuristics. Lastly, we propose a methodology to assess the appropriateness of dynamic scheduling in this context.
Fichier principal
Vignette du fichier
ijpp.pdf (1.16 Mo) Télécharger le fichier
Origine Fichiers produits par l'(les) auteur(s)
Loading...

Dates et versions

hal-01087067 , version 1 (12-01-2016)

Identifiants

Citer

Paul-Antoine Arras, Didier Fuin, Emmanuel Jeannot, Arthur Stoutchinin, Samuel Thibault. List Scheduling in Embedded Systems Under Memory Constraints. International Journal of Parallel Programming, 2015, 43 (6), pp.1103-1128. ⟨10.1007/s10766-014-0338-1⟩. ⟨hal-01087067⟩

Collections

CNRS INRIA INRIA2
413 Consultations
281 Téléchargements

Altmetric

Partager

More