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Journal Articles World Academy of Science, Engineering and Technology Year : 2009

Hardware Description Language Design of Sigma-Delta Fractional-N Phase-Locked Loop for Wireless Applications

Abstract

This paper discusses a systematic design of a Sigma-Delta fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.
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Dates and versions

hal-00947400 , version 1 (15-02-2014)

Identifiers

  • HAL Id : hal-00947400 , version 1

Cite

Ahmed El Oualkadi, Abdellah Ait Ouahman. Hardware Description Language Design of Sigma-Delta Fractional-N Phase-Locked Loop for Wireless Applications. World Academy of Science, Engineering and Technology, 2009, 28, pp.1035-1042. ⟨hal-00947400⟩
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