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Reports (Research Report) Year : 2013

Efficient Out-of-Order Execution of Guarded ISAs

Nathanaël Prémillieu
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André Seznec


ARM ISA based processors are no longer low-cost low-power processors. Nowadays ARM ISA based processor manufacturers are struggling to implement medium-end to high-end processor cores which implies implementing a state-of-the-art out-of-order execution engine. Unfortunately providing efficient out-of-order execution on legacy ARM codes may be quite challenging due to guarded instructions. Predicting the guarded instructions addresses the main serialization impact associated with guarded instructions execution and the multiple definition problem. Moreover guard prediction allows to use a global branch-and-guard history predictor to predict both branches and guards, often improving branch prediction accuracy. Unfortunately such a global branch-and-guard history predictor requires the systematic use of guard predictions. In that case, poor guard prediction accuracy would lead to poor overall performance on some applications. Building on top of recent advances in branch prediction and confidence estimation, we propose a hybrid branch and guard predictor, combining a global branch history component and global branch-and-guard history component. The potential gain or loss due to the systematic use of guard prediction is dynamically evaluated at run-time. Two computing modes are enabled: systematic guard prediction use and high confidence only guard prediction use. Our experiments show that on most applications, an overwhelming majority of guarded instructions are predicted. Therefore a simple but relatively inefficient hardware solution can be used to execute the few unpredicted guarded instructions. Significant performance benefits are observed on most applications while applications with poorly predictable guards do not suffer from performance loss.
Les processeurs exécutant le jeu d'instructions ARM ne sont omniprésents. La demande de puissance de calcul est telle qu'aujourd'hui toutes les techniques jusqu'à pr\'sent réserv\'des á la haute performance sont utilisées pour le design de ces processeurs. Dans ce rapport, nous montrons que le jeu d'instruction prédiqué de ARM n'est pas un obstacle á la mise en oeuvre efficace de l'exécution dans le désordre.
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Dates and versions

hal-00910335 , version 1 (29-11-2013)


  • HAL Id : hal-00910335 , version 1


Nathanaël Prémillieu, André Seznec. Efficient Out-of-Order Execution of Guarded ISAs. [Research Report] RR-8406, INRIA. 2013, pp.24. ⟨hal-00910335⟩
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