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Conference Papers Year : 2013

Verifying MARTE/CCSL Mode Behaviors Using UPPAAL


In the development of safety-critical embedded systems, the ability to formally analyze system behavior models, based on timing and causality, helps the designer to get insight into the systems overall timing behavior. To support the design and analysis of real-time embedded systems, the UML modeling profile MARTE provides CCSL - a time model and a clock constraint specification language. CCSL is an expressive language that supports specification of both logical and chronometric constraints for MARTE models. On the other hand, semantic frameworks such as timed automata provide verification support for real-time systems. To address the challenge of verifying CCSL-based behavior models, in this paper, we propose a technique for transforming MARTE/CCSL mode behaviors into Timed Automata for model-checking using the UPPAAL tool. This enables verification of both logical and chronometric properties of the system, which has not been possible before. We demonstrate the proposed transformation and verification approach using two relevant examples of real-time embedded systems.

Dates and versions

hal-00866477 , version 1 (26-09-2013)



Jagadish Suryadevara, Cristina Seceleanu, Frédéric Mallet, Paul Pettersson. Verifying MARTE/CCSL Mode Behaviors Using UPPAAL. SEFM 2013 - 11th International Conference on Software Engineering and Formal Methods, Sep 2013, Madrid, Spain. pp.1-15, ⟨10.1007/978-3-642-40561-7_1⟩. ⟨hal-00866477⟩
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