State-based representation of CCSL operators
Abstract
The UML Profile for Modeling and Analysis of Real-Time and Embedded systems promises a general modeling framework to design and analyze systems. Lots of works have been published on the modeling capabilities offered by MARTE, much less on verification techniques supported. The Clock Constraint Specification Language (CCSL), first introduced as a companion language for MARTE, was devised to offer a formal support to conduct causal and temporal analyses on MARTE models. This work introduces formally a state-based semantics for CCSL operators.
Domains
Embedded Systems
Origin : Files produced by the author(s)
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