A Hierarchical Approach for Load Balancing on Parallel Multi-core Systems - Inria - Institut national de recherche en sciences et technologies du numérique
Communication Dans Un Congrès Année : 2012

A Hierarchical Approach for Load Balancing on Parallel Multi-core Systems

Résumé

Multi-core compute nodes with non-uniform memory access (NUMA) are now a common architecture in the assembly of large-scale parallel machines. On these machines, in addition to the network communication costs, the memory access costs within a compute node are also asymmetric. Ignoring this can lead to an increase in the data movement costs. Therefore, to fully exploit the potential of these nodes and reduce data access costs, it becomes crucial to have a complete view of the machine topology (i.e. the compute node topology and the interconnection network among the nodes). Furthermore, the parallel application behavior has an important role in determining how to utilize the machine efficiently. In this paper, we propose a hierarchical load balancing approach to improve the performance of applications on parallel multi-core systems. We introduce NucoLB, a topology-aware load balancer that focuses on redistributing work while reducing communication costs among and within compute nodes. NucoLB takes the asymmetric memory access costs present on NUMA multi-core compute nodes, the interconnection network overheads, and the application communication patterns into account in its balancing decisions. We have implemented NucoLB using the Charm++ parallel runtime system and evaluated its performance. Results show that our load balancer improves performance up to 20% when compared to state-of-the-art load balancers on three different NUMA parallel machines.

Dates et versions

hal-00788012 , version 1 (13-02-2013)

Identifiants

Citer

Laércio Pilla, Christiane Pousa Ribeiro, Daniel Cordeiro, Chao Mei, Abhinav Bhatele, et al.. A Hierarchical Approach for Load Balancing on Parallel Multi-core Systems. ICPP 2012 - 41st IEEE International Conference on Parallel Processing, Sep 2012, Pittsburgh, Pennsylvania, United States. pp.118-127, ⟨10.1109/ICPP.2012.9⟩. ⟨hal-00788012⟩
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