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Conference Papers Year : 2012

Fast Dynamic Translation Using LLVM On Multi-Core Hosts

Zhang Zuyu
  • Function : Author
  • PersonId : 935473
Vania Joloboff
Xinlei Zhou
  • Function : Author
  • PersonId : 935474
Claude Helmstetter
  • Function : Author
  • PersonId : 857075


In the development of embedded systems, Instruction-Set Simulators (ISS) plays an important role. When using an ISS, simulation speed is a significant issue. In this paper, we present experiments and comparison between several dynamic translation techniques. In addition to an existing technique which serves as a reference, we have developed a new on-the-fly translation technique using the LLVM open-source compiler infrastructure to enhance simulation speed. This dynamic translation technique translates hot basic blocks of the target instruction set into LLVM bitcode, then compiles LLVM bitcode into host binary code using the LLVM Just-In-Time (JIT) compiler. As the translation time using LLVM increases to the detriment of the overall simulation speed, we also present a mixed mode, where only the frequently executed chunks of code are compiled. This translation technique was then extended to support larger translation units compared to the previous, Finally the paper ends with presentation of an orthogonal solution to dispatch dynamic translation to a translation server to take advantage of multi-processor hosts.
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Dates and versions

hal-00777156 , version 1 (17-01-2013)


  • HAL Id : hal-00777156 , version 1


Zhang Zuyu, Vania Joloboff, Xinlei Zhou, Claude Helmstetter. Fast Dynamic Translation Using LLVM On Multi-Core Hosts. 5th Workshop on Architectural and Microarchitectural Support for Binary Translation (AMAS-BT), Intel Corporation, Jun 2012, Portland, Oregon, United States. ⟨hal-00777156⟩
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