Random numbers are required in many applications such as cryptography, telecommunications, digital simulations or VLSI circuits testing. Pseudo random number generators (PRNGs) usually lead to very high throughput with software and hardware implementations. But they are based on deterministic algorithms. This is a problem in many security applications. True random number generators (TRNGs) are based on the extraction of some physical noise in hardware implementations (jitter variations, meta-stability, radioactive decay...). For ASIC and FPGA circuits, a widely used TRNG solution is based on oscillator sampling. The physical noise source is the jitter (the phase deviation) produced by one or several free running oscillators. One part of the jitter is produced by random noise but another part is produced by deterministic noise (power supply, clock or chip activity, cross talk...). So the randomness quality depends on noise source characteristics but also on other parameters such as TRNG architecture, implementation details and many environment parameters (circuit temperature, power supply, in-chip activity, electromagnetic radiations, clock signal quality). All those parameters may be used to attack the TRNG, reduce the quality of the produced random sequence and then reduce the security of the complete system (e.g. weak key). In this talk, we will introduce context and standard architectures for TRNG circuits. Statistical methods for randomness quality evaluation will be recalled. Then we will detail two ASIC circuits (130 nm technology) designed in the CAIRN team for TRNGs based on oscillator sampling with on-line and real-time evaluation of the quality of TRNG output. FPGA versions will also be presented and discussed. The on-line and real-time monitoring of the generated random sequence is useful to prevent randomness quality reduction due to environment variations or physical attacks against the TRNG.