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Conference Papers Year : 2004

DSP Code Generation with Optimized Data Word-Length Selection

Abstract

Digital signal processing applications are implemented in embedded systems with fixed-point arithmetic to minimize the cost and the power consumption. To reduce the application time-to-market,methodologies for automatically determining the fixed-point specification are required. In this paper, a new methodology for optimizing the fixed-point specification in the case of software implementation is described. Especially, the technique proposed to select the data word-length under a computation accuracy constraint is detailed. Indeed, the latest DSP generation allows to manipulate a wide range of data types through sub-word parallelism and multiple-precision instructions. In comparison with the existing methodologies, the DSP architecture is completely taken into account to optimize the execution time under accuracy constraint. Moreover, the computation accuracy evaluation is based on an analytical approach which allows to minimize the optimization time of the fixed-point specification. The experimental results underline the efficiency of our approach.

Dates and versions

inria-00482942 , version 1 (12-05-2010)

Identifiers

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Daniel Menard, Olivier Sentieys. DSP Code Generation with Optimized Data Word-Length Selection. 8th International Workshop on Software and Compilers for Embedded Systems SCOPES 2004, Sep 2004, Amsterdam, Netherlands. ⟨10.1007/b99901⟩. ⟨inria-00482942⟩
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