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Communication Dans Un Congrès Année : 2023

In-Place Multicore SIMD Fast Fourier Transforms

Benoît Dupont de Dinechin
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Julien Hascoet
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Résumé

We revisit 1D Fast Fourier Transforms (FFT) implementation approaches in the context of compute units composed of multiple cores with SIMD ISA extensions and sharing a multi-banked local memory. A main constraint is to spare use of local memory, which motivates us to use in-place FFT implementations and to generate the twiddle factors with trigonometric recurrences. A key objective is to maximize bandwidth of the multi-banked local memory system by ensuring that cores issue maximum-width aligned non-temporal SIMD accesses. We propose combining the SIMD lane-slicing and sample partitioning techniques to derive multicore FFT implementations that do not require matrix transpositions and only involve one stage of bit-reverse unscrambling. This approach is demonstrated on the Kalray MPPA3 processor compute unit, where it outperforms the classic six-step algorithm for multicore FFT implementation.
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Dates et versions

hal-04240798 , version 1 (13-10-2023)

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  • HAL Id : hal-04240798 , version 1

Citer

Benoît Dupont de Dinechin, Julien Hascoet, Orégane Desrentes. In-Place Multicore SIMD Fast Fourier Transforms. HPEC 2023 - 27th Annual IEEE High Performance Extreme Computing Virtual Conference, Sep 2023, Virtual conference, United States. ⟨hal-04240798⟩
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