Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis - Inria - Institut national de recherche en sciences et technologies du numérique
Communication Dans Un Congrès Année : 2022

Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis

Résumé

The RISC-V ecosystem is quickly growing and has gained a lot of traction in the FPGA community, as it permits free customization of both ISA and microarchitectural features. However, the design of the corresponding micro-architecture is costly and error-prone. We address this issue by providing a flow capable of automatically synthesizing pipelined micro-architectures directly from an Instruction Set Simulator in C/C++. Our flow is based on HLS technology and bridges part of the gap between Instruction Set Processor design flows and High-Level Synthesis tools by taking advantage of speculative loop pipelining. Our results show that our flow is general enough to support a variety of ISA and micro-architectural extensions, and is capable of producing circuits that are competitive with manually designed cores.
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Dates et versions

hal-03828841 , version 1 (25-10-2022)

Identifiants

Citer

Jean-Michel Gorius, Simon Rokicki, Steven Derrien. Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis. FPT 2022 - International Conference on Field Programmable Technology, Dec 2022, Honk Kong / Hybrid, Hong Kong SAR China. pp.1-6, ⟨10.1109/ICFPT56656.2022.9974478⟩. ⟨hal-03828841⟩
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