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Journal Articles IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Year : 2020

Toward Speculative Loop Pipelining for High-Level Synthesis

Abstract

Loop pipelining is a key optimization in modern HLS tools for synthesizing efficient hardware datap-aths. Existing techniques for automatic loop pipelining are limited by static analysis that cannot precisely analyze loops with data-dependent control-flow and/or memory accesses. We propose a technique for speculative loop pipelining that handles both control-flow and memory speculations in a unified manner. Our approach is entirely expressed at the source-level, allowing a seamless integration to development flows using HLS. Our evaluation shows significant improvement in throughput over standard loop pipelining.
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Dates and versions

hal-02949516 , version 1 (25-09-2020)

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Cite

Steven Derrien, Thibaut Marty, Simon Rokicki, Tomofumi Yuki. Toward Speculative Loop Pipelining for High-Level Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39 (11), pp.4229 - 4239. ⟨10.1109/TCAD.2020.3012866⟩. ⟨hal-02949516⟩
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