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Conference Papers Year : 2020

Fast Cross-Layer Vulnerability Analysis of Complex Hardware Designs

Abstract

Simulation-based fault injection is commonly used to estimate system vulnerability. Existing approaches either partially model the fault masking capabilities of the system under study, losing accuracy, or require prohibitive estimation times. This work proposes a vulnerability analysis approach that combines gate-level fault injection with microarchitecturelevel Cycle-Accurate and Bit-Accurate simulation, achieving low estimation times. Single and multi-bit faults both in sequential and combinational logic are considered and fault masking is modeled at gate-level, microarchitecture-level and application-level, maintaining accuracy. Our case-study is a RISC-V processor. Obtained results show a more than 8% reduction in masked errors, increasing more than 55% system failures compared to standard a fault injection approach.
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Dates and versions

hal-02927455 , version 1 (29-01-2021)

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Joseph Paturel, Angeliki Kritikakou, Olivier Sentieys. Fast Cross-Layer Vulnerability Analysis of Complex Hardware Designs. ISVLSI 2020 - IEEE Computer Society Annual Symposium on VLSI, Jul 2020, Limassol, Cyprus. pp.328-333, ⟨10.1109/ISVLSI49217.2020.00067⟩. ⟨hal-02927455⟩
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