Which Verification for Soft Error Detection? - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Conference Papers Year :

Which Verification for Soft Error Detection?


Many methods are available to detect silent errors in high-performance computing (HPC) applications. Each comes with a given cost and recall (fraction of all errors that are actually detected). The main contribution of this paper is to characterize the optimal computational pattern for an application: which detector(s) to use, how many detectors of each type to use, together with the length of the work segment that precedes each of them. We conduct a comprehensive complexity analysis of this optimization problem, showing NP-completeness and designing an FPTAS (Fully Polynomial-Time Approximation Scheme). On the practical side, we provide a greedy algorithm whose performance is shown to be close to the optimal for a realistic set of evaluation scenarios.
Fichier principal
Vignette du fichier
hipc.pdf (583.53 Ko) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

hal-01252382 , version 1 (07-01-2016)


  • HAL Id : hal-01252382 , version 1


Leonardo Bautista-Gomez, Anne Benoit, Aurélien Cavelan, Saurabh K. Raina, Yves Robert, et al.. Which Verification for Soft Error Detection?. High Performance Computing 2015, Dec 2015, Bangalore, India. ⟨hal-01252382⟩
137 View
134 Download


Gmail Facebook Twitter LinkedIn More