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Conference Papers Year : 2016

ProteusTM: Abstraction Meets Performance in Transactional Memory

Abstract

The Transactional Memory (TM) paradigm promises to greatly simplify the development of concurrent applications. This led, over the years, to the creation of a plethora of TM implementations delivering wide ranges of performance across workloads. Yet, no universal TM implementation fits each and every workload. In fact, the best TM in a given workload can reveal to be disastrous for another one. This forces developers to face the complex task of tuning TM implementations, which significantly hampers the wide adoption of TMs. In this paper, we address the challenge of automatically identifying the best TM implementation for a given workload. Our proposed system, ProteusTM, hides behind the TM interface a large library of implementations. Under the hood, it leverages an innovative, multi-dimensional online optimization scheme, combining two popular machine learning techniques: Collaborative Filtering and Bayesian Optimization. We integrated ProteusTM in GCC and demonstrated its ability to switch TM implementations and adapt several configuration parameters (e.g., number of threads). We extensively evaluated ProteusTM, obtaining average performance < 3% from optimal, and gains up to 100 over static alternatives.
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Dates and versions

hal-01250459 , version 1 (04-01-2016)

Identifiers

Cite

Diego Didona, Nuno Diegues, Rachid Guerraoui, Anne-Marie Kermarrec, Ricardo Neves, et al.. ProteusTM: Abstraction Meets Performance in Transactional Memory. Twenty First International Conference on Architectural Support for Programming Languages and Operating Systems, Apr 2016, Atlanta, United States. ⟨10.1145/2872362.2872385⟩. ⟨hal-01250459⟩
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