Adding a single state memory optimally accelerates symmetric linear maps - Inria - Institut national de recherche en sciences et technologies du numérique
Article Dans Une Revue IEEE Transactions on Automatic Control Année : 2016

Adding a single state memory optimally accelerates symmetric linear maps

Alain Sarlette

Résumé

Previous papers have proposed to add memory registers to the dynamics of discrete-time linear systems in order to accelerate their convergence. In particular, it has been proved that adding one memory slot per agent allows faster convergence towards average consensus. We here prove that this situation cannot be improved by adding more memory slots, when the knowledge about the self-adjoint linear map to be accelerated reduces to bounds on its extreme eigenvalues.
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Dates et versions

hal-01093907 , version 1 (05-01-2015)
hal-01093907 , version 2 (28-12-2015)

Identifiants

Citer

Alain Sarlette. Adding a single state memory optimally accelerates symmetric linear maps. IEEE Transactions on Automatic Control, 2016, 61 (11), pp.3533. ⟨10.1109/TAC.2016.2516247⟩. ⟨hal-01093907v2⟩
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