An Energy-Efficient FPGA-Based Packet Processing Framework - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Conference Papers Year : 2010

An Energy-Efficient FPGA-Based Packet Processing Framework


Modern packet processing hardware (e.g. IPv6-supported routers) demands high processing power, while it also should be power-efficient. In this paper we present an architecture for high-speed packet processing with a hierarchical chip-level power management that minimizes the energy consumption of the system. In particular, we present a modeling framework that provides an easy way to create new networking applications on an FPGA based board. The development environment consists of a modeling environment, where the new application is modeled in SystemC. Furthermore, our power management is modeled and tested against different traffic loads through extensive simulation analysis. Our results show that our proposed solution can help to reduce the energy consumption significantly in a wide range of traffic scenarios.
Fichier principal
Vignette du fichier
030_scalopes_eunice2010_final.pdf (407.79 Ko) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

hal-01056561 , version 1 (20-08-2014)





Daniel Horvath, Imre Bertalan, Istvan Moldován, Tuan Anh Trinh. An Energy-Efficient FPGA-Based Packet Processing Framework. 16th EUNICE/IFIP WG 6.6 Workshop on Networked Services and Applications - Engineering, Control and Management (EUNICE), Jun 2010, Trondheim, Norway. pp.31-40, ⟨10.1007/978-3-642-13971-0_4⟩. ⟨hal-01056561⟩
97 View
408 Download



Gmail Facebook Twitter LinkedIn More