Wireless Sensor Networks (WSNs) are relatively new and challenging research area for embedded design automation. Engineering a WSN node hardware is a difficult job as the design must satisfy several constraints. Among these constraints, overall energy consumption and node size, are the two most significant constraints. WSN node platforms have until recently been designed using off-the-shelf low-power microprocessors (MCUs), even though energy profile of these MCUs is not suitable for ultra low-power sensor nodes. On the other hand, WSN-specific hardware accelerators have also been proposed that have excellent energy profile but lack in flexibility, need higher design efforts and have huge non-recurring engineering (NRE) costs. In this work, we propose an automated system level design flow for an intermediate approach, based on the concept of data path merging (DPM) where several hardware accelerators (called micro-tasks) share a common customized data path, to have an improvement in flexibility and silicon area with possible increase in dynamic power consumption for the control/processing part of the sensor node targeted for field programmable gate array (FPGA)-based implementation. Our experiments show that component-level DPM yields to savings from 20%, to 75% for various FPGA resources like I/O ports, area for combinational and sequential logic, and static power consumption.