Formal Verification of Hardware Synthesis - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Conference Papers Year : 2013

Formal Verification of Hardware Synthesis

Abstract

We report on the implementation of a certified compiler for a high-level hardware description language (HDL) called Fe-Si (FEatherweight SynthesIs). Fe-Si is a simplified version of Bluespec, an HDL based on a notion of guarded atomic actions. Fe-Si is defined as a dependently typed deep embedding in Coq. The target language of the compiler corresponds to a synthesisable subset of Verilog or VHDL. A key aspect of our approach is that input programs to the compiler can be defined and proved correct inside Coq. Then, we use extraction and a Verilog back-end (written in OCaml) to get a certified version of a hardware design.

Keywords

Fichier principal
Vignette du fichier
main.pdf (194.06 Ko) Télécharger le fichier
Origin : Files produced by the author(s)
Loading...

Dates and versions

hal-00776876 , version 1 (20-01-2013)

Identifiers

Cite

Thomas Braibant, Adam Chlipala. Formal Verification of Hardware Synthesis. Computer Aided Verification - 25th International Conference, Jul 2013, Saint Petersburg, Russia. pp.213-228, ⟨10.1007/978-3-642-39799-8_14⟩. ⟨hal-00776876⟩

Collections

INRIA INRIA2
238 View
389 Download

Altmetric

Share

Gmail Facebook X LinkedIn More