Power gating has emerged as a promising technique for reduction of leakage current in sub-100 nm CMOS circuits. To identify power gating opportunities within a system, logic circuits must be charac- terized for design overheads they present when power gating structures are inserted. In this paper, models are developed to quantify two mode transition overheads: wakeup time and wakeup energy using basic circuit parameters. First, a method to determine steady-state virtual-supply voltage in active mode is described and hence a model for virtual-supply voltage is presented based on certain heuristic approximations. Further, analytical expressions are derived for estimation of wakeup time and wakeup energy for a power-gated logic cluster using the proposed model. A key contribution of this paper is a study of nonlinear resistance based view of leakage current profiles of logic circuits. Finally, the application of proposed models to ISCAS85 benchmark circuits is demonstrated while also analyzing the accuracy of approximations used.