Power Consumption Model for Partial Dynamic Reconfiguration
Résumé
In the context of embedded systems development, two important challenges are the efficient use of silicon area and the energy consumption minimization. Hardware accelerated tasks allow to reduce energy consumption of several orders of magnitude, compared to software execution, but these tasks require silicon area and consume power even when they are unused (idle power). Dynamic and Partial Reconfiguration (DPR) brings, to System-on-Chip architectures, an interesting answer by allowing to share a piece of silicon surface between different dedicated accelerators and thus brings the opportunity to reduce power consumption. Nevertheless, many parameters like reconfiguration overhead, accelerator area and performance tradeoff, idle power consumption, etc. make power consumption gain difficult to evaluate. In order to take good implementation choices, it is important to have a precise power and energy consumption estimation of the partial reconfiguration process. In this context, this paper presents a detailed investigation of power consumption of a DPR process using Xilinx ICAP reconfiguration controller. From these results we propose three power models with different complexity/accuracy tradeoffs which helps to analyze the benefits of using accelerated and dynamically reconfigurable tasks in comparison with classical static configuration or full software execution
Mots clés
system-on-chip
reconfigurable architectures
power aware computing
performance evaluation
energy consumption
embedded systems
circuit complexity
power consumption model
embedded systems development
energy consumption minimization
hardware acceleration
energy consumption reduction
dynamic and partial reconfiguration
DPR
system-on-chip architectures
power consumption reduction
reconfiguration overhead
accelerator area
performance tradeoff
idle power consumption
power consumption gain evaluation
DPR process
Xilinx ICAP reconfiguration controller
complexity tradeoff
accuracy tradeoff
Power demand
Field programmable gate arrays
Clocks
Power measurement
Digital signal processing
Memory management
Hardware