Scripts Use for the Synthesis and the Simulation of VHDL Circuits and Evaluation of the Power Consumption
Résumé
This document presents a way of using scripts for the synthesis or the simulation of VHDL hardware components. Moreover it explains the estimation of the power consumption of such circuits that can be evaluated by XPower. The use of such scripts allows to automate the procedures and to deal with many circuits without repeating the same tasks several times. The steps presented in this document are based on scripts that are published under the GNU GPL, they can be used and modified as wanted by the user.
Domaines
Autre [cs.OH]Origine | Fichiers produits par l'(les) auteur(s) |
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