Multiplierless Processing Element for Non-Power-of-Two FFTs - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Preprints, Working Papers, ... Year : 2018

Multiplierless Processing Element for Non-Power-of-Two FFTs


This paper presents hardware-efficient building blocks for non-power-of-two Fast Fourier transform (FFT) algorithms. A reconfigurable unified multiplierless mixed radix-2/3/4/5 FFT design is proposed. In addition, standalone designs for the computation of the multiplierless radix-3 and radix-5 processing elements are illustrated. These architectures are based on Wingorad Fourier transform algorithm , which uses constant multipliers instead of general complex-valued multipli-ers. In this paper we propose to further reduce the hardware complexity by replacing the constant multipliers by shift-and-add structures. In addition, we show that the unified architecture is achieved by adding only a small number of multiplexers. The implementation results for field-programmable gate arrays (FPGAs) with Look-Up Table based logic are provided. In all of them, the proposed designs achieve significant reduction in area (around 30%) with respect to state of the art.
Fichier principal
Vignette du fichier
multiplierless-processing-element.pdf (1.1 Mo) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

hal-01690832 , version 1 (23-01-2018)


  • HAL Id : hal-01690832 , version 1


Fahad Qureshi, Anastasia Volkova, Thibault Hilaire, Jarmo Takala. Multiplierless Processing Element for Non-Power-of-Two FFTs. 2018. ⟨hal-01690832⟩
381 View
323 Download


Gmail Facebook X LinkedIn More