Compact FPGA Implementations of the Five SHA-3 Finalists - Inria - Institut national de recherche en sciences et technologies du numérique
Communication Dans Un Congrès Année : 2011

Compact FPGA Implementations of the Five SHA-3 Finalists

Résumé

Allowing good performances on different platforms is an important criteria for the selection of the future sha-3 standard. In this paper, we consider the compact implementations of blake, Grøstl, jh, Keccak and Skein on recent fpga devices. Our results bring an interesting complement to existing analyzes, as most previous works on fpga implementations of the sha-3 candidates were optimized for high throughput applications. Following recent guidelines for the fair comparison of hardware architectures, we put forward clear trends for the selection of the future standard. First, compact fpga implementations of Keccak are less efficient than their high throughput counterparts. Second, Grøstl shows interesting performances in this setting, in particular in terms of throughput over area ratio. Third, the remaining candidates are comparably suitable for compact fpga implementations, with some slight contrasts (in area cost and throughput).
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Dates et versions

hal-01596314 , version 1 (27-09-2017)

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Stéphanie Kerckhof, François Durvaux, Nicolas Veyrat-Charvillon, Francesco Regazzoni, Guerric Dormale, et al.. Compact FPGA Implementations of the Five SHA-3 Finalists. 10th Smart Card Research and Advanced Applications (CARDIS), Sep 2011, Leuven, Belgium. pp.217-233, ⟨10.1007/978-3-642-27257-8_14⟩. ⟨hal-01596314⟩
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