Memory-Side Acceleration for XML Parsing - Inria - Institut national de recherche en sciences et technologies du numérique
Communication Dans Un Congrès Année : 2011

Memory-Side Acceleration for XML Parsing

Jie Tang
  • Fonction : Auteur
  • PersonId : 1017422
Shaoshan Liu
  • Fonction : Auteur
  • PersonId : 1017423
Zhimin Gu
  • Fonction : Auteur
  • PersonId : 1017424
Chen Liu
  • Fonction : Auteur
  • PersonId : 1017425
Jean-Luc Gaudiot

Résumé

As Extensible Markup Language (XML) becomes prevalent in cloud computing environments, it also introduces significant performance overheads. In this paper, we analyze the performance of XML parsing, identify that a significant fraction of the performance overhead is indeed incurred by memory data loading. To address this problem, we propose implementing memory-side acceleration on top of computation-side acceleration of XML parsing. To this end, we study the impact of memory-side acceleration on performance, and evaluate its implementation feasibility including bus bandwidth utilization, hardware cost, and energy consumption. Our results show that this technique is able to improve performance by up to 20% as well as produce up to 12.77% of energy saving when implemented in 32 nm technology.
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Dates et versions

hal-01593022 , version 1 (25-09-2017)

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Jie Tang, Shaoshan Liu, Zhimin Gu, Chen Liu, Jean-Luc Gaudiot. Memory-Side Acceleration for XML Parsing. 8th Network and Parallel Computing (NPC), Oct 2011, Changsha,, China. pp.277-292, ⟨10.1007/978-3-642-24403-2_22⟩. ⟨hal-01593022⟩
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