A 100dB SFDR 0.5V pk-pk Band-Pass DAC Implemented on a Low Voltage CMOS Process - Inria - Institut national de recherche en sciences et technologies du numérique
Communication Dans Un Congrès Année : 2012

A 100dB SFDR 0.5V pk-pk Band-Pass DAC Implemented on a Low Voltage CMOS Process

Résumé

Direct Digital Synthesis (DDS) systems generate fine frequency resolution signals over a broad spectrum that are used in a wide variety of applications such as multi-mode RF, communications, measurements and test. A high performance DDS band-pass Digital to Analog Converter (DAC) architecture and implementation is presented that delivers high spectral purity over a narrow-band response. The low power D/A Converter is portable to standard CMOS processes and designed to achieve over 100dB narrow-band SFDR performance using Sigma-Delta (∑ Δ) modulation and multi-bit current steering techniques. A 3rd order digital ∑ Δ modulator is combined with a 4th order digital Dynamic Element Matching (DEM) block to shape the noise while calibrating for process mismatch variations. A low silicon area output stage is used to deliver a high performance specification.
Fichier principal
Vignette du fichier
978-3-642-32770-4_9_Chapter.pdf (1.85 Mo) Télécharger le fichier
Origine Fichiers produits par l'(les) auteur(s)
Loading...

Dates et versions

hal-01519770 , version 1 (09-05-2017)

Licence

Identifiants

Citer

Brendan Mullane, Vincent O’brien. A 100dB SFDR 0.5V pk-pk Band-Pass DAC Implemented on a Low Voltage CMOS Process. 19th International Conference on Very Large Scale Integration (VLSISOC), Oct 2011, Hong Kong, China. pp.144-157, ⟨10.1007/978-3-642-32770-4_9⟩. ⟨hal-01519770⟩
250 Consultations
390 Téléchargements

Altmetric

Partager

More