More than 30% of the total energy consumed in the U.S. is attributed to industrial sector which motivated improvements in energy efficiency of manufacturing processes and entire factories. Semiconductor fabrication (fab) represents an interesting challenge for energy efficiency because of their relatively high energy consumption to process a unit mass of material. The focus of this paper is to develop an energy-aware analytical model based on queuing theory that has re-entrant network structure commonly found in fabs to analyze the impact of reducing idle power consumption in individual equipment. The proposed analytical model based on BCMP network for re-entrant lines has the same mathematical form as serial lines and is tested for using detailed simulation of a generic CMOS fab with three processing steps. Results show that the energy consumption predicted by the analytical model differs from simulation typically within 10% and worst case of 14%, in the tested cases.