A significant number of cryptographic architectures rely on the efficient and resilient implementation of the Montgomery modular multiplier. One of the most used attacks on cryptographic implementations is based on Differential Power Analysis (DPA) or one of its variants. In this paper, a specially adjusted Latch-less Asynchronous Charge Sharing Logic (LACSL) is developed to inherently defend such architecture against DPA attacks. The proposed logic provides input data independent low-power/energy consumption which is attributed to interleaved charge sharing stages with non-static elements involved in the data path. A 32-bit LACSL Montgomery Multiplier (case study) is extensively tested through HSPICE simulations and great consistency in power/energy consumption is achieved. The normalized energy deviation and normalized standard deviation are only 0.048 and 0.011, respectively. Compared with the original ACSL implementation, besides the impressive energy coherence, 42% energy saving is demonstrated plus that the leakage power is 3.5 times smaller. Furthermore, the scalability of the proposed multiplier is explored where 64-bit, 128-bit and 256-bit designs are implemented. Again, great energy consistency is found with the highest deviation being 0.5%. The proposed techniques can be easily migrated to other low-power circuits for which accurate power/energy models can be built, independent of the input data profile. Keywords—asynchronous; modular arithmetic; charge sharing logic; side channel attack; input data independent energy circuits