A Worst Case Performance Model for TDM Virtual Circuit in NoCs - Inria - Institut national de recherche en sciences et technologies du numérique
Communication Dans Un Congrès Année : 2010

A Worst Case Performance Model for TDM Virtual Circuit in NoCs

Résumé

In Network-on-Chip (NoC), Time-Division-Mutiplexing (TDM) Virtual Circuit (VC) is well recognized as being capable to provide guaranteed services in both latency and bandwidth. We propose a method of modeling TDM based VC by using Network Calculus. We derive a tight upper bound of end-to-end delay and buffer requirement for indivdual VC. The performance analysis using Latency-Rate server is also presented in comparsion with our Performance model for TDM Virtual Circuit in NoCs (Pemvin). We conducted experiments on comparing Pemvin to the Latency-Rate server model. Our experiment results show the improvement of Pemvin on tightening the upper bound of end-to-end delay and buffer requirement.
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Dates et versions

hal-01054964 , version 1 (11-08-2014)

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Zhipeng Chen, Axel Jantsch. A Worst Case Performance Model for TDM Virtual Circuit in NoCs. IFIP International Conference on Network and Parallel Computing (NPC), Sep 2010, Zhengzhou, China. pp.452-461, ⟨10.1007/978-3-642-15672-4_38⟩. ⟨hal-01054964⟩
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