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sorted by
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Towards a Systematic, Pragmatic and Architecture-Aware Program Optimization Process for Complex ProcessorsACM Supercomputing Conference (SC), 2004, Pittsburgh, Pennsylvania, United States
Conference papers
hal-01257302v1
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Characterization of Legal Transformations Sequences1st MicroGrid workshop, 2005, Amsterdam, Netherlands
Conference papers
hal-01257300v1
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A Fast SystemC EngineDesign, Automation and Test in Europe, Feb 2004, Paris/France
Conference papers
inria-00001108v1
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CMA: Chip Multi-AcceleratorIEEE Symposium on Application Specific Processors, SASP 2010., Jun 2010, Anaheim, CA, United States
Conference papers
inria-00633586v1
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Budgeted Region Sampling (BeeRS): Do Not Separate Sampling From Warm-Up, And Then Spend Wisely Your Simulation Budget5th IEEE International Symposium on Signal Processing and Information Technology, Dec 2005, Athens, Greece
Conference papers
inria-00001061v2
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MicroLib: A Case for the Quantitative Comparison of Micro-ArchitectureMechanismsWorkshop on Duplicating, Deconstructing, and Debunking, Jun 2004, Munich, Germany
Conference papers
inria-00001109v1
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Facilitating the Exploration of Compositions of Program Transformations[Research Report] RR-5114, INRIA. 2004
Reports
inria-00071468v1
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Automatic Abstraction and Fault Tolerance in Cortical Microachitectures38th ACM/IEEE International Symposium on Computer Architecture, ISCA 2011, Jun 2011, San Jose, CA, United States
Conference papers
inria-00579771v1
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Stream and Memory Hierarchy Design for Multi-Purpose Accelerators1st Workshop on SoC Architecture, Accelerators and Workloads (SAW-1), Jan 2010, Bangalore, India
Conference papers
inria-00633580v1
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Putting Polyhedral Loop Transformations to Work[Research Report] RR-4902, INRIA. 2003
Reports
inria-00071681v1
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Characterizing Self-Developing Biological Neural Networks: A First Step Towards their Application To Computing SystemsLecture Notes in Computer Science, 2005, 3512, pp.306-317
Journal articles
inria-00000024v1
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Milepost GCC: Machine Learning Enabled Self-tuning CompilerInternational Journal of Parallel Programming, 2011, 39, pp.296-327. ⟨10.1007/s10766-010-0161-2⟩
Journal articles
hal-00685276v1
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MILEPOST GCC: machine learning based research compilerGCC Summit, Jun 2008, Ottawa, Canada
Conference papers
inria-00294704v1
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CAPSULE: Hardware-Assisted Parallel Execution of Component-Based ProgramsMICRO-39, Dec 2006, Orlando, Florida, USA
Conference papers
inria-00103184v1
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Facilitating the Search for Compositions of Program Transformationsics # (ICS), 2005, Boston, Massachusetts, Unknown Region. pp.151--160
Conference papers
hal-01257296v1
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A Sampling Method Focusing on PracticalityIEEE Micro, 2006
Journal articles
inria-00158808v2
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Processeurs : la nouvelle donne par Olivier Temam. Forces et faiblesses de l'Europe : entretien avec Panagiotis Tsarchopoulos, propos recueillis par Dominique ChouchanLes Cahiers de l'INRIA - La Recherche, 2009, Le hasard au coeur de la vie, 434 octobre 2009
Journal articles
inria-00522268v1
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Semi-Automatic Composition of Loop Transformations for Deep Parallelism and Memory HierarchiesInternational Journal of Parallel Programming, 2006, 34 (3), pp.261--317. ⟨10.1007/s10766-006-0012-3⟩
Journal articles
hal-01257288v1
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A Polyhedral Approach to Ease the Composition of Program TransformationsEuro-Par, 2004, Pisa, Italy. pp.292--303
Conference papers
hal-01257301v1
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Bioinformatique : de la cellule à la puce. Alchimistes de l'informatique, entretien avec Hugues Berry et Olivier Temam, propos recueillis par Dominique Chouchan.Les Cahiers de l'INRIA - La Recherche, 2008, Homo Erectus Sort D'afrique, 419 mai 2008
Journal articles
inria-00546805v1
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Practical Run-time Adaptation with Procedure Cloning to Enable Continuous Collective CompilationProc. of the 5þ GCC Developper's Summit, 2007, Ottawa, Ontario, Unknown Region
Conference papers
hal-01257279v1
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Modeling Self-Developing Biological Neural NetworksNeurocomputing, 2007, 70 (16-18), pp.2723-2734. ⟨10.1016/j.neucom.2006.06.013⟩
Journal articles
inria-00149082v1
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A Practical Method For Quickly Evaluating Program OptimizationsHiPEAC 2005 -- 1st International Conference on High Performance Embedded Architectures \& Compilers, Nov 2005, Barcelona, Spain, France
Conference papers
inria-00001054v1
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Chaos in computer performanceChaos: An Interdisciplinary Journal of Nonlinear Science, 2006, 16 (1), pp.013110. ⟨10.1063/1.2159147⟩
Journal articles
inria-00000109v2
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Quick and practical run-time evaluation of multiple program optimizationsFirst International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2005, Nov 2005, Barcelona, Spain
Conference papers
inria-00084110v1
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IDDCA: A New Clustering Approach For SamplingMoBS: Workshop on Modeling, Benchmarking, and Simulation, Jun 2005, Madison, Wisconsin
Conference papers
inria-00001062v1
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AP+SOMT: Agent-Programming Combined with Self-Organized Multi-ThreadingWorkshop on Complexity-Effective Design at ISCA 31, Jun 2004, Munich/Germany
Conference papers
inria-00001107v1
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Collective OptimizationHiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_5⟩
Conference papers
inria-00445326v1
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The MHAOTEU Toolset16th IMACS world congress 2000 on scientific computation, applied mathematics and simulation (IMACS'2000), Ecole polytechnique fédérale de Lausanne, Aug 2000, Lausanne, Switzerland. pp.6
Conference papers
hal-00648211v1
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Characterizing the behavior of sparse algorithms on caches[Research Report] RR-1666, INRIA. 1992
Reports
inria-00074891v1
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