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Rapport Année : 2000

Hardware-friendly neural computation of symmetric boolean functions

Bernard Girau

Résumé

The theoretical and practical framework of Field Programmable Neural Arrays has been defined to reconcile simple hardware topologies with complex neural architectures: FPNAs lead to powerful neural models whose original data exchange scheme allows to use hardware-friendly neural topologies. This report addresses preliminary results in the study of the computation power of FPNAs. The computation of symmetric boolean functions (e.g. the n-dimensional parity problem) is taken as a textbook example. The FPNA concept allows successive topology simplifications of standard neural models for such functions, so that the number of weights is reduced with a factor up to n with respect to previous works.
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Dates et versions

inria-00107867 , version 1 (19-10-2006)

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  • HAL Id : inria-00107867 , version 1

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Bernard Girau. Hardware-friendly neural computation of symmetric boolean functions. [Intern report] A00-R-024 || girau00n, 2000, 8 p. ⟨inria-00107867⟩
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