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Reports (Research Report) Year : 1993

About cache associativity in low-cost shared memory multi-microprocessors

Abstract

In 1993, sizes of on-chip caches on current commercial microprocessors range from 16 Kbytes to 36 Kbytes. These microprocessors can be directly usedin the design of a low cost single-bus shared memory multiprocessors with-out using any second-level cache. In this paper, we explore theviability of such a multi-microprocessor. Simulations results clearly establish that performance of such a system will be quite poor if on-chip caches are direct-mapped. On the other hand, when the on-chip caches are partially associative, the achieved level of performance is quite promising. In particular, two recently proposed innovative cache structures, the skewed associative cache organization and the semi-unified cache organization are shown to work fine.

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Other [cs.OH]
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Dates and versions

inria-00077193 , version 1 (29-05-2006)

Identifiers

  • HAL Id : inria-00077193 , version 1

Cite

Nathalie Drach, Alain Gefflaut, Philippe Joubert, André Seznec. About cache associativity in low-cost shared memory multi-microprocessors. [Research Report] RR-2083, INRIA. 1993. ⟨inria-00077193⟩
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