Skewed-associative caches - Inria - Institut national de recherche en sciences et technologies du numérique Accéder directement au contenu
Rapport (Rapport De Recherche) Année : 1992

Skewed-associative caches

André Seznec
François Bodin
  • Fonction : Auteur
  • PersonId : 950104

Résumé

During the past decade, microprocessors potential performance has increased at a tremendous rate using RISC concept, higher and higher clock frequencies and parallel / pipelined instruction issuing. As the gap between the main memory access time and the potential average instruction time is always increasing, it has become very important to improve the behavior of the caches, particularly when no secondary cache is used (i.e. on all low cost microprocessor systems ). In order to improve cache hit ratios, set-associative caches are used in most of the new superscalar microprocessors. In this paper, we present a new organization for a multi-bank cache : the skewed-associative cache. Skewed-associative caches have a better behavior than set-associative caches : typically a two-banks skewed-associative cache has the hardware complexity of a two-way set-associative cache, but exhibits the same hit ratio as a four-way set associative cache of the same size.

Domaines

Autre [cs.OH]
Fichier principal
Vignette du fichier
RR-1655.pdf (860.33 Ko) Télécharger le fichier

Dates et versions

inria-00074902 , version 1 (24-05-2006)

Identifiants

  • HAL Id : inria-00074902 , version 1

Citer

André Seznec, François Bodin. Skewed-associative caches. [Research Report] RR-1655, INRIA. 1992. ⟨inria-00074902⟩
651 Consultations
374 Téléchargements

Partager

Gmail Facebook X LinkedIn More