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Reports (Research Report) Year : 1993

An integrated 2D systolic array for spelling correction

Dominique Lavenier

Abstract

This paper presents a fully integrated spelling co-processor for speeding up the character string comparison process. The chip we present is architectured around a banded 2-D systolic array consisting of 69 processors and is able to process more than 2 million of words per second. The high regularity of the chip has been exploited for investigating a design methodology based on the automated generation of a representative subcircuit : the kernel.

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Other [cs.OH]
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Dates and versions

inria-00074685 , version 1 (24-05-2006)

Identifiers

  • HAL Id : inria-00074685 , version 1

Cite

Dominique Lavenier. An integrated 2D systolic array for spelling correction. [Research Report] RR-1987, INRIA. 1993. ⟨inria-00074685⟩
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