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Reports (Research Report) Year : 1993

Algorithm engineering and VLSI design


The task of producing a VLSI architecture that will solve a given problem contains many design decisions. The effects of these decisions on the final design are often difficult to quantify. We will compare three different implementations of a systolic architecture for solving the knapsack problem using the dynamic programming method. The design decisions involved and the engineering of the algorithm (altering the algorithm to improve its implementation) are highlighted and their effects on the resulting implementation are discussed. We will also relate the design area and timing to the parameters of the knapsack problem. We derive [??]) as estimations of area and circuit timing complexity of the memory control. We will eliminate the influence of the dominant knapsack parameter (the capacity c) and replace it by the maximum weight [??]. This is of crucial importance for a realistic and efficient VLSI implementation of this problem since in practice [??]2 c.


Other [cs.OH]
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Dates and versions

inria-00074614 , version 1 (24-05-2006)


  • HAL Id : inria-00074614 , version 1


William P. Marnane, Rumen Andonov. Algorithm engineering and VLSI design. [Research Report] RR-2058, INRIA. 1993. ⟨inria-00074614⟩
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