Energy reduction potential of a phase-based cache resizing scheme for embedded systems - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Reports (Research Report) Year : 2003

Energy reduction potential of a phase-based cache resizing scheme for embedded systems

Abstract

Managing the energy-performance tradeoff has become a major challenge on embedded systems. The cache hierarchy is a typical example of such a design target where this tradeoff plays a central role. With the increasing level of integration density, a cache can feature several billions of transistors, consuming a large proportion of the energy. In the same time however, it also allows to considerably improve the performance. Configurable caches are becoming the de-facto solution to deal efficiently with that problem. Such caches are equipped with artifacts that enable one to resize it dynamically. In the context of embedded systems, however, many of these artifacts restrict the configurability at the application level. We propose in this paper to modify the structure of a configurable cache to offer embedded compilers the opportunity to reconfigure it according to a program dynamic phase, rather than on a per-application basis. We show in our experimental results that the proposed scheme has a potential for improving the compiler effectiveness to reduce the energy consumption, while not excessively degrading the performance.

Domains

Other [cs.OH]
Fichier principal
Vignette du fichier
RR-5036.pdf (1.14 Mo) Télécharger le fichier

Dates and versions

inria-00071548 , version 1 (23-05-2006)

Identifiers

  • HAL Id : inria-00071548 , version 1

Cite

Gilles Pokam, François Bodin. Energy reduction potential of a phase-based cache resizing scheme for embedded systems. [Research Report] RR-5036, INRIA. 2003. ⟨inria-00071548⟩
66 View
67 Download

Share

Gmail Facebook Twitter LinkedIn More