FPGA Configuration of Intensive Multimedia Processing Tasks Modeled in UML
Abstract
Recent research have demonstrate interests in a codesign framework that allows description refinement at different abstraction level. We have proposed such a framework that allows SoC resources allocation for regular and repetitive tasks found in intensive multimedia applications. Nevertheless, the framework does not directly target reconfigurable architectures, the difficult job of placing and routing an application on a FPGA being postponed to a dedicated tool. In order to limit the number of synthesis on this external tool, we propose an algorithm that, from a high level description of an intensive multimedia application, estimates the resource usages on a given FPGA architecture. This algorithm makes use of a simple mathematical formalism issued from case study implementations.
Domains
Other [cs.OH]
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