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Journal Articles Concurrency and Computation: Practice and Experience Year : 2023

Combining reduction with synchronization barrier on multi‐core processors

Abstract

With the rise of multi-core processors with a large number of cores, the need for shared memory reduction that performs efficiently on a large number of cores is more pressing. Efficient shared memory reduction on these multi-core processors will help share memory programs be more efficient. In this article, we propose a reduction method combined with a barrier method that uses SIMD read/write instructions to combine barrier signaling and reduction value to minimize memory/cache traffic between cores, thereby reducing barrier latency. We compare different barriers and reduction methods on three multi-core processors and show that the proposed combining barrier/reduction methods are 4 and 3.5 times faster than respectively GCC 11.1 and Intel 21.2 OpenMP 4.5 reduction.
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Dates and versions

hal-03948901 , version 1 (16-02-2022)
hal-03948901 , version 2 (14-03-2023)

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Aboul‐karim Mohamed El Maarouf, Luc Giraud, Abdou Guermouche, Thomas Guignon. Combining reduction with synchronization barrier on multi‐core processors. Concurrency and Computation: Practice and Experience, 2023, 35 (1), pp.e7402. ⟨10.1002/cpe.7402⟩. ⟨hal-03948901v2⟩
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