A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Eﬀiciency at 10-mA Load

. A synthesizable digital LDO implemented with standard-cell-based digital design ﬂow is proposed. The di ﬀ erence between output and reference voltages is converted into delay di ﬀ erence using inverter chains as voltage-controlled delay lines, then compared in the time-domain. Since the time-domain di ﬀ erence is straightforwardly captured by a simple DFF-based phase detector, the proposed LDO does not need an analog voltage comparator, which requires careful manual design. All the components in the LDO can be described with Verilog codes based on their speciﬁcations, and placed-and-routed with a commercial EDA tool. This automated layout design relaxes the burden and time of implementation, and enhances process portability. The proposed LDO implemented in a 65nm standard CMOS technology occupies 0 : 015mm 2 area. With 10 : 4MHz internal clock, the tracking response of the LDO to 200mV switching in the reference voltage is (cid:24) 4 : 5 (cid:181) s and the transient response to 5mA change in the load current is (cid:24) 6 : 6 (cid:181) s. At 10mA load current, the quiescent current consumed by the LDO core is as low as 35 : 2 (cid:181) A, which leads to 99 : 6% current e ﬃ ciency.


Introduction
Along with the exponential advancement of process technologies, performance of LSI circuits rapidly improves and many functional building blocks such as analog, logic, RF, memory block, etc. can be integrated on a chip, which have brought system-on-a-chip (SoC) era.Meanwhile, in order to reduce power consumption as indicated by the scaling law, power supply voltages have been lowered.In addition, it is desirable that a power supply of each functional block is independently tuned according to the changing operating condition so as to have the optimal power efficiency.The on-chip voltage regulation is essential for this purpose, because off-chip voltage regulators require large PCB area, which leads to increase in cost.For those reasons, efficient, tunable, fast-transient and on-chip power sources are in great demand for SoC, hence low-dropout (LDO) regulators are now widely used.As shown in Fig. 1(a), conventional LDOs have been designed with analog circuits and employed an error amplifier, a driver amplifier and an analog pass transistor to provide voltage regulation with negative feedback.When the supply voltage is high enough, they exhibit high current efficiency, fast transient response, high power supply rejection and small output ripple [1][2][3][4].In addition, their area occupation could be smaller than other power management circuits such as switching regulators, because they do not require large inductors.However, they have difficulty in operating at low supply voltage, since amplifiers cannot sustain their dynamic range and high gain under such a situation.To solve this issue, the digital implementations of LDOs shown in Fig. 1(b) has been proposed [5][6][7][8][9][10][11][12][13][14][15].A typical digital LDO has a digital controller made of logic gates that controls the number of turned-on PMOS switches at output stage, and employs an analog voltage comparator to detect the difference between reference and feedback voltages.Thus digital LDOs can eliminate amplifiers and operate under a low supply voltage.Moreover, since they are constucted mainly from digital logic gates, their performance can be easily improved by process downscaling and clock boosting.
A voltage comparator, however, often requires careful manual design so as to minimize the voltage offset between two inputs.Thus even digital LDOs also require sophisticated analog design flows, which is often time-consuming.A digital design flow, on the other hand, requires much less design effort, because its layout design is automated.Since circuit implementation in digital design flows is based on RTL source codes, the circuits that have the similar specification can be made easily even when the used process technologies are updated.Thus recently many analog circuits such as analog-to-digital converters (ADC) [16] or phase-locked loops (PLL) [17] are designed through digital automated flow, in order to take advantage of the relaxed design burden and process portability.Hence we have been motivated to implement LDOs, one of the indispensable blocks for SoCs, in digital design flows.
In order to relax the burden of manual analog designs, this paper proposes a synthesizable digital LDO, whose preliminary results have been presented in [18].By utilizing voltage-to-time conversion, the proposed LDO has a suitable architecture for standard-cell-based automatic place and route (P&R).

Architecture
One of the design issues in constructing an LDO with standard cells is an implementation of a voltage comparison unit.Reference [16] reported that an analog voltage comparator can be implemented with 3-input NAND gates.Such comparators can be easily designed, but they suffer from the random systemtic offset owing to the randomness of the automatic P&R.Thus the single comparator made of NAND gates is not suitable for precise voltage comparison.The PLL-like LDO in [6] employs voltage-controlled ring oscillators in order to convert the voltage difference into the phase difference.However, this architecture is not preferable because a voltage-controlled ring oscillator has an integral characteristic that adds a pole to the system, which deteriorates the stability of the loop.Moreover, voltage-controlled ring oscillators might be a cause to increase the current consumption of the voltage comparison unit.Some digital LDOs utilize voltage-to-time converters (VTC) and time-to-digital converters (TDC) [7,8], so that they exclude analog voltage comparators.Although a TDC can be composed of digital logic cells, its layout implementation actually requires manual design because its linearity is very sensitive to the parasitic capacitance of its layout pattern.Hence we propose to use a simple bang-bang detector, in order to relax the complexity of the layout and eliminate the systematic offset even when the layout is automatically placed and routed.
Our proposed LDO shown in Fig. 2 employs voltage-controlled delay lines (VCDL), and the difference between the reference and the output voltages are converted into the time-domain.The proposed LDO consists of two inverter chains, a bang-bang phase detector, a digital controller, a PMOS switch array, and an output capacitor.Though for this prototype a dedicated ring oscillator is used as an internal clock source and a pulse generator, these clock and pulse signals can be replaced by a clock for other blocks on the SoC.The digital controller generates 128-bit-width thermometer code from 1-bit output from the bang-bang phase detector to control the switches.The PMOS switch array has parallelly-aligned 128 PMOS transistors, all of which have the same size.Each gate of the switch is connected to each bit of the thermometer code from the digital controller.The two inverter chains have the same structure, which has a series connection of 128 inverters.As shown in Fig. 3, the bang-bang phase detector is simply composed of a D-FF and a buffer.The buffer is connected to the clock input of the D-FF to compensate the setup time of the D-FF.As shown in Fig. 4, the internal clock and pulse generator is composed of inverters, D-FFs, and multiplexers for frequency tuning.The output capacitor is assembled off-chip.Once the switch PMOS transistor cell is added to a standard-cell library, all cells needed to compose the proposed LDO are included in the library and the LDO can be generated from Verilog gate-level netlists and synthesized with a P&R tool.
The layout of the PMOS switch has to follow the design rules for standard cells so that it can be placed and routed by the P&R tool.Fig. 5 shows an outline of the PMOS switch cell layout.It is designed just by removing the NMOS transistor from the inverter cell for ease of the additional cell layout.Thus, the size of the PMOS switch cell is equal to that of the inverter cell.The operation of the proposed LDO is described as follows.As shown in Fig. 2, the two inverter chains are powered by V re f and V out , respectively.An identical pulse train from the internal pulse generator enters into them at the same time.The inverter chains work as VCDLs.In other words, the inverter chains convert the voltage difference between V re f and V out into the delay difference that is compared by the phase detector.Based on the phase detector output, the digital controller changes the number of turned-on PMOS switches.
Fig. 6.Signal flow graph of the digital controller that includes proportional and integral paths.
Fig. 6 shows the signal flow graph of the digital controller.The operation of the digital controller is expressed by the following discrete-time difference equations.
The digital controller includes proportional and integral paths.Output[n] is 7-bit binary.
Then the binary output is decoded into thermometer code so that the number of turned-on PMOS switches can be controlled one by one.When V out is higher than V re f , the phase detector output becomes HIGH and the digital controller decreases the number of turned-on switches.On the contrary, when V out is lower than V re f , the phase detector output becomes LOW and the digital controller increases the number of turned-on switches.In this way V out approaches to V re f .As the divider and the multiplexer is attached to the internal clock and pulse generator, in this prototype the clock frequency can be easily tuned by the multiplexer for test purpose.The components other than the inverter chains are powered by V in .The HIGH-level voltage of the pulse trains which travel through the inverter chains are equal to their power source voltage, V re f or V out .Therefore, if V re f is lower than the logic threshold voltage of the phase detector powered by V in , the phase detector cannot be driven by the pulse from the inverter chain powered by V re f .Thus, the lower limit of V re f is determined by the logic threshold voltage of the standard cells powered by V in .

Transfer Function of the Control Loop
Fig. 7 shows the signal flow graph of the proposed LDO.The comparison unit composed of inverter chains and a D-FF generates an error sample.Since the comparison is done based on the pulse train which is the same signal as the clock, one clock delay occurs here at every sample.As previously described, the digital controller has proportional and integral paths.In order to investigate the loop stability in continuous-time domain, the approximation below is applied: where T s represents the sampling period.The transfer function of the digital controller is thus approximated as follows: The output stage is composed of the switch array, the output capacitor, and the effective resistance.I pmos is the current through a single PMOS switch.According to [9], the effective resistance R l can be approximated as V out /I load .Using (3) and ( 5), the continuous-time open-loop transfer function G(s) is given by When I load is small, R l becomes big so that R −1 l ≪ sC out .Then, G(s) approximates If K p = 0, the poles of the closed-loop transfer function are close to the imaginary axis, and thus the system tends to be unstable.To avoid oscillation, we add the proportional gain K p to the digital controller.Fig. 8 shows the bode plots of the open loop transfer function with small I load of 100 µA for K P = 0 and K p = 1, respectively.When K p = 0, the phase margin is 17 • , whereas it is 27 • when K p = 1, which suppresses the abrupt phase change around 1 MHz.

Design Procedure of the Proposed LDO
This section explains the design procedure of the proposed LDO.Fig. 9 shows the design flow diagram.The explanation follows the step numbers shown in Fig. 9. 0) The PMOS switch cell is designed in advance and added to the standard-cell library.
1) The specification of the circuit, such as maximum load current or reference voltage, is set.Based on this specification, the number of the PMOS switches in the switch array and the output bit width of the digital controller are determined.
2) The RTL Verilog code of the digital controller is prepared, then logically synthesized to have the gate-level Verilog netlist.3) The gate-level Verilog netlists of other components, such as the inverter chain, the phase detector, the switch array, and the internal clock and pulse generator are generated by a dedicated script.Examples of the gate-level Verilog description is shown in Fig. 10.Since each building block has simple standard-cell-based structure, the gate-level netlist generation is simply implemented.For example, the switch array is constructed only by the parallel PMOS switch cells, and thus its gate-level netlist is generated easily by the script according to the specification.4) The layout of each building block is individually placed and routed by a P&R tool.This is because they have different power supplies; the two inverter chains are powered by V out or V re f respectively, and the other blocks are powered by V in .We use the same layout for both of the two inverter chains, so that there is little systematic offset in the voltage comparison unit.5) All the layouts are connected together.It takes few hours to generate the whole layout of the proposed LDO from scratch, which is much less time than that in the case for the conventional LDO design with analog flows.

Prototype Implementation and Measurement Results
Based on the architecture described in the previous section, the prototype of the proposed LDO is fabricated in a 65 nm standard CMOS technology.Fig. 11 shows the chip photo.The active area of the proposed LDO is 0.015 µm 2 .Fig. 12 shows the measured tracking response of V out with 10.4 MHz clock when V re f , which is externally supplied in this measurement, switches between 600 mV and 800 mV.Here, I load and C out is 10 mA and 220 pF, respectively.When V re f changes from 600 mV to 800 mV, the settling time is 4.5 µs, whereas it is 4.4 µs when V re f changes from 800 mV to 600 mV.Fig. 13 shows the measured transient response of V out with 10.4 MHz clock when I load changes between 5 mA and 10 mA.V re f of 800 mV and C out of 220 pF are used in this experiment.When I load changes from 5 mA to 10 mA, the  settling time is 6.6 µs and the undershoot is 303 mV.When I load changes from 10 mA to 5 mA, the settling time is 6.0 µs and the overshoot is 126 mV.Since the operation region of PMOS temporarily enters into saturation region when the undershoot occurs while it does not for the case of overshoot, the waveforms of V out transient become different in these two cases.
The overall current consumption with 10.4 MHz clock and I load of 10 mA is 282 µA including the current consumed at the internal clock and pulse generator, which is not essential in the actual use because it can be substituted by an internal clock for other functional blocks on the SoC.Based on the circuit simulation result, the LDO core consumes 12.5 % of the total current as shown in Fig. 14.Thus, the quiescent current of the LDO core is assumed to be 35.2µA, which leads to 99.6 % current efficiency.
In the proposed architecture, V re f is used as a power source of a VCDL.Hence, V re f is required to supply current to drive the VCDL for voltage comparison.Fig. 15 shows the current consumption from V re f versus the frequency of the pulse train, which is equal to CLK, with V re f of 800 mV and I load of 10 mA.The pulse is sent from the internal oscillator, and its frequency is tuned by the multiplexer.Typically, when the pulse frequency is 10.4 MHz, the current consumption from V re f is 10.6 µA.According to Fig. 15, the current consumption of V re f is proportional to the pulse frequency.When the pulse frequency is set high in order to have the fast transient response, V re f is required to supply more current.
Table 1 shows performance comparison to prior digital LDOs.This work realizes a competitive current efficiency and FOM T with synthesizable architecture, while others cannot be fully synthesizable and need manual designs.Owing to the automated design flow of this work, if needed the maximum load current I load,max can be easily increased by adding more PMOS switches, at the expense of the increase in the area and the quiescent current.

Conclusion
This paper proposes a synthesizable digital LDO that is designed by a P&R tool.In the proposed LDO, by using inverter chains as VCDLs, the difference between the output and the reference voltages is converted into the delay difference that can be compared  by a phase detector.The voltage control loop is all composed of standard cells and synthesizable, which drastically relaxes the design burden.The prototype is fabricated in a 65 nm standard CMOS technology with 0.015 mm 2 area occupation.According to the measurement results of the prototype, with 10.4 MHz clock and C out of 220 pF the tracking response time when V re f switches between 600 mV and 800 mV is ∼4.5 µs with I load of 10 mA, and the transient response time when I load changes between 5 mA and 10 mA is ∼6.6 µs with V re f of 800 mV.The quiescent current consumed by the LDO core is as low as 35.2 µA at 10 mA load current, which leads to 99.6 % current efficiency.In our prototype, V re f needs to supply 10.6 µA current when the pulse frequency is 10.4 MHz.
In this paper, we used a PMOS switch cell made from an inverter cell.However, this customized PMOS switch cell can be substituted by a tri-state inverter cell [15] or a tri-state buffer cell.If the inputs of these cells are tied to LOW (in the case of tri-state inverters) or HIGH (in the case of tri-state buffers), the output PMOS transistors can be controlled by the tri-state control inputs.Thus, if these cells are included in the standard cell library, a fully standard-cell based synthesizble LDO can be realized and the design burden would be more relaxed.

Acknowledgment
This work is partly supported by JSPS KAKENHI Grant Number 17H03244, and is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc., Cadence Design Systems, Inc., and Mentor Graphics, Inc.

Fig. 1 .
Fig. 1.LDO architectures.(a) Conventional analog LDO has a simple architecture, and includes an error amplifier, a driver amplifier and an analog pass transistor.(b) Digital LDO includes a comparator, a digital controller made of logic gates, and parallel pass transistors.

Fig. 5 .
Fig. 5. (a) An inverter cell and (b) an additional PMOS transistor cell for the switch array.

Fig. 13 .Fig. 14 .
Fig. 13.Measured transient response of V out when I load changes between 5 mA and 10 mA with 10.4 MHz-clock, V re f of 800 mV and C out of 220 pF.

Fig. 15 .
Fig. 15.Current consumption from V re f versus the frequency of the pulse train.
Design flow of the proposed circuit.