Design and Optimization of Multiple-Mesh Clock Network - Inria - Institut national de recherche en sciences et technologies du numérique Access content directly
Conference Papers Year : 2015

Design and Optimization of Multiple-Mesh Clock Network


A clock mesh, in which clock signals are shorted at mesh grid, is less susceptible to on-chip process variation, and so it has widely been studied recently for a clock network of smaller skew. A practical design may require more than one mesh primarily because of hierarchical clock gating architecture; a single mesh, however, can also support the same architecture after some hierarchies are removed but at the cost of gating efficiency. We experimentally compare multiple- and single-mesh using a few test circuits, and show that the former consumes smaller clock power (16.3 %) but exhibits larger clock skew (10.2 ps) and longer clock wirelength (21.7 %). We continue to study how multiple meshes should be floorplanned on the layout, specifically whether or not we allow the overlaps among meshes. The choice is translated into different physical design strategy, and causes different amount of clock skew, critical path delay, clock wirelength, and clock power consumption, which we experimentally evaluate. We give at last the comparison of clock skew variation for each mesh implementation and clock tree, and show that floorplanning of multiple meshes helps to reduce the variation of clock skew.
Fichier principal
Vignette du fichier
371768_1_En_3_Chapter.pdf (913.49 Ko) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

hal-01383727 , version 1 (19-10-2016)





Jinwook Jung, Dongsoo Lee, Youngsoo Shin. Design and Optimization of Multiple-Mesh Clock Network. 22th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC 2014), Oct 2014, Playa del Carmen, Mexico. pp.39-57, ⟨10.1007/978-3-319-25279-7_3⟩. ⟨hal-01383727⟩
165 View
159 Download



Gmail Facebook X LinkedIn More