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Conference Papers Year : 2017

Automating the pipeline of arithmetic datapaths

Abstract

This article presents the new framework for semi-automatic circuit pipelining that will be used in future releases of the FloPoCo generator. From a single description of an operator or datapath, optimized implementations are obtained automatically for a wide range of FPGA targets and a wide range of frequency/latency trade-offs. Compared to previous versions of FloPoCo, the level of abstraction has been raised, enabling easier development, shorter generator code, and better pipeline optimization. The proposed approach is also more flexible than fully automatic pipelining approaches based on retiming: In the proposed technique, the incremental construction of the pipeline along with the circuit graph enables architectural design decisions that depend on the pipeline. These allow pipeline-dependent changes to the circuit graph for finer optimization.
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Dates and versions

hal-01373937 , version 1 (29-09-2016)
hal-01373937 , version 2 (16-12-2016)

Identifiers

  • HAL Id : hal-01373937 , version 2

Cite

Matei Istoan, Florent de Dinechin. Automating the pipeline of arithmetic datapaths. Design, Automation & Test in Europe Conference & Exhibition (DATE 2017), Mar 2017, Lausanne, Switzerland. ⟨hal-01373937v2⟩
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